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ADuC7060
IRQCONN
IRQSTAN Register
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits. The first to enable nesting and
prioritization of IRQ interrupts the other to enable nesting and
prioritization of FIQ interrupts.
If these bits are cleared, then FIQs and IRQs can still be used,
but it is not possible to nest IRQs or FIQs. Neither is it possible
Name:
Address:
Default value:
Access:
IRQSTAN
0xFFFF003C
0x00000000
Read and write
to set an interrupt source priority level. In this default state, an
FIQ does have a higher priority than an IRQ.
Table 71. IRQSTAN MMR Bit Designations
Bit Name Description
IRQCONN Register
Name:
IRQCONN
Address:
0xFFFF0030
31:8
7:0
Reserved
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
Default value:
Access:
0x00000000
Read and write
FIQVEC
The FIQ interrupt vector register, FIQVEC, points to a memory
Table 70. IRQCONN MMR Bit Designations
address containing a pointer to the interrupt service routine of
the currently active FIQ. This register should be read only when
Bit
31:2
1
Name
Reserved
ENFIQN
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
an FIQ occurs and FIQ interrupt nesting has been enabled by
setting Bit 1 of the IRQCONN register.
FIQVEC Register
Name:
FIQVEC
0
ENIRQN
Setting this bit to 1 enables nesting of IRQ
Address:
0xFFFF011C
interrupts. Clearing this bit means no nesting
IRQSTAN
or prioritization of IRQs is allowed.
Default value:
Access:
0x00000000
Read only
If IRQCONN.0 is asserted and IRQVEC is read, then one of
these bits is asserted. The bit that asserts depends on the
Table 72. FIQVEC MMR Bit Designations
Initial
priority of the IRQ. If the IRQ is of Priority 0 then Bit 0 asserts,
Priority 1 then Bit 1 asserts, and so forth. When a bit is set in
this register, all interrupts of that priority and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
Bit
31:23
22:7
6:2
Type
Read only
R/W
Value
0
0
0
Description
Always read as 0.
IRQBASE register value.
Highest priority FIQ source. This is
cleared first. It is possible to clear only one bit at a time. For
example, if this register is set to 0x09, writing 0xFF changes the
register to 0x08, and writing 0xFF a second time changes the
register to 0x00.
a value between 0 to 19 that
represents the possible interrupt
sources. For example, if the
highest currently active FIQ is
Timer1, then these bits are
[01000].
1:0
Reserved
0
Reserved bits.
Rev. 0 | Page 58 of 100
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